An Asynchronous Register Bypass Transformation

A register specification typically states that in each cycle there is a possible read followed by a possible write; the sequence is strict. A register core with a separate read and write port is more efficient, because it can read and write to different locations simultaneously, and hence in one cycle. In the Caltech MiniMIPS processor, a control structure was added to such a register core, so that it implements the desired specification

Design Rules for Non-Atomic Implementations of PRS

Martin Synthesis yields quasi--delay-insensitive (QDI) circuits, expressed in production--rule-set (PRS) form. Under an atomic circuit evaluation model, these circuits are provably correct. However, not all physical circuit implementations provide the atomic transitions needed to satisfy the atomic circuit model. This can cause operational failures in real circuits, as we illustrate. Nonetheless, circuits with non-atomic transitions can faithfully implement the atomic circuit model when combined with a few simple slewtime constraints. To generalize this, we present a non-atomic circuit model, and we prove that any non-atomic circuit satisfying the slewtime constraints implements the atomic circuit model. To synthesize correct physical circuits, therefore, one can use Martin Synthesis assuming atomicity, and then physically implement the resulting circuit using the slewtime constraints as design rules

A Theory of Constant Et^2 CMOS Circuits

In a digital CMOS circuit, used digitally, the dynamic energy consumption of a single pulldowm state has the form CV^2, while the current i is kV^2, and the delay t is CV/i, where C is an output capacitance, V is the supply voltage, and k is a transconductance parameter

Stable Production Rule Sets are Deterministic

Production Rule Sets (PRS) are a digital event-based model for CMOS circuits; stable production rule sets are those in which in every execution, every enabled rule remains enabled until it is executed. It has been conjectured that stable production rule sets are determinstic, meaning in particular that they cannot implement arbiters, and that the sequence of values sent on any channel is independent of the execution. In this paper, we prove these facts rigorously, directly from first principles. We also propose improvements to PRS testing tools based on the resulting theory

Pipelining Saturated Accumulation

Aggressive pipelining and spatial parallelism allow integrated circuits (e.g., custom VLSI, ASICs, and FPGAs) to achieve high throughput on many Digital Signal Processing applications. However, cyclic data dependencies in the computation can limit parallelism and reduce the efficiency and speed of an implementation. Saturated accumulation is an important example where such a cycle limits the throughput of signal processing applications. We show how to reformulate saturated addition as an associative operation so that we can use a parallel-prefix calculation to perform saturated accumulation at any data rate supported by the device. This allows us, for example, to design a 16-bit saturated accumulator which can operate at 280 MHz on a Xilinx Spartan-3(XC3S-5000-4) FPGA, the maximum frequency supported by the component's DCM

The Lutonium: A Sub-Nanojoule Asynchronous 8051 Microcontroller

We describe the Lutonium, an asynchronous 8051 microcontroller designed for low Et/sup 2/. In 0.18 /spl mu/m CMOS, at nominal 1.8 V, we expect a performance of 0.5 nJ per instruction at 200 MIPS. At 0.5 V, we expect 4 MIPS and 40 pJ/instruction, corresponding to 25,000 MIPS/Watt. We describe the structure of a fine-grain pipeline optimized for Et/sup 2/ efficiency, some of the peripherals implementation, and the advantages of an asynchronous implementation of a deep-sleep mechanism

What is deterministic CHP, and is slack elasticity that useful?

This paper addresses the issue of slack elasticity in distributed computation, as defined by the Caltech Asynchronous VLSI group. We show with a counterexample that slack elasticity is not sufficient for process decomposition. We give criteria which imply slack elasticity and which are sufficient for several forms of process decomposition, and present a hierarchy of determinism

Stable Production Rule Sets are Deterministic

Production Rule Sets (PRS) are a digital event-based model for CMOS circuit

Rigorous Analog Verification of Asynchronous Circuits

This thesis shows that rigorous verification of some analog implementation of any Quasi-Delay-Insensitive (QDI) asynchronous circuit is possible. That is, we show that in an accurate analog model, any behavior will adhere to the digital computation specifications under any possible noise and environment timing. Unlike a traditional simulation, we can analyze all of the infinitely many possible analog behaviors, in a time linear in the circuit size. A problem that arises in asynchronous circuit design is that the analog implementations of digital computations do not in general exhibit all properties demanded by the digital model assumed in circuit construction. For example, the digital model is atomic, in a sense we define. By contrast, analog models are non-atomic, and, as a result, we can give examples of real circuits with operational failures. There exist other attributes of analog models which can cause failures, and no complete classification exists. Ultimately there is only one way to solve this problem: we must show that all possible analog behaviors obey the atomic model. We focus on CMOS implementations, and the associated accepted bulk-scale model. Given any canonically-generated implementation of a general computation, we can rigorously verify it. The only exception to this rule is that restoring delay elements must be inserted into some implementations (fortunately, this change has no semantic effect on QDI circuits, by definition). Our theorem guarantees that when any possible analog behavior is properly observed, we obtain a valid, atomic digital execution. Several rigorous verifications have been produced, including one for an asynchronous pipeline circuit with dual-rail data